In the current Ethernet network or link (hereinafter, occasionally referred to simply as Ethernet), network equipments forming the Ethernet are operated with mutually independent clocks. Accordingly, network equipments on the Ethernet naturally transmit/receive data to/from network equipments on an SDH (Synchronous Digital Hierarchy) or SONET (Synchronous Optical Network) (hereinafter, generally represented by SDH) network or link with mutually independent clocks.
FIG. 11 depicts a related art network equipment used in an SDH link or Ethernet. This network equipment NE corresponds to e.g. a network equipment NE2 in a network configuration example as depicted in FIG. 1, in which taking the example of FIG. 1, an SDH unit SU#1 that is a line interface unit LIU is connected to an SDH unit (not depicted) in a network equipment NE1; an SDH unit SU#2 is connected to an SDH unit (not depicted) in a network equipment NE4; and Ethernet units EU#1 and EU#2 (hereinafter, occasionally referred to as a reference symbol EU) forming a line interface unit LIU are connected to an Ethernet unit (not depicted) in e.g. network terminal equipments NTE1 and NTE2.
Then, the SDH unit SU#1 receives a signal having a line clock speed of e.g. 155.52 MHz (for STM1) (or 622.04 MHz (for STM4) or 2488.16 MHz (for STM16)) from the network equipment NE1, in which a frequency divider FD divides the frequency of the received signal at a ratio of 1/8 to generate line clocks LCLw and LCLp of 19.4 MHz to be transmitted to timing processors TC (W) and TC (P).
It is to be noted that “W” indicates a working side and “P” indicates a protection side, so that hereinafter the line clocks LCLw and LCLp may be generally referred to as a line clock LCL and the timing processors TC (W) and TC (P) may also be generally referred to as a timing processor TC.
The SDH unit SU#2 connected to the network equipment NE4 generates a line clock LCL as with the above SDH unit SU#1 to be transmitted to the timing processor TC.
The working and protection timing processors TC have a function of selecting a clock of the best quality among the line clocks LCL [19.44 MHz] transmitted from the SDH units SU#1 and SU#2 (hereinafter, occasionally referred to as a reference symbol SU), respectively generating equipment (element) clocks ECLw and ECLp (hereinafter, occasionally referred to as a reference symbol ECL) of 38.88 MHz forming a master clock for overall network equipments NE, synchronized with the selected clock at a phase locked loop portion PLL1 to be distributed to the SDH units SU#1 and SU#2, where the equipment clocks ECLw and ECLp are respectively provided to packet switches SW (W) and SW (P) as well. The SDH unit SU converts the equipment clock [38.88 MHz] into the line clock of 155.52 MHz at a phase locked loop portion PLL2 and outputs a transmission signal based on the line clock.
The above selection of the clock quality is determined based on SSM (Synchronization Status Message) that is a data indicating the quality transmitted through serial buses SB (W) and SB (P) (hereinafter, occasionally referred to as a reference symbol SB) interconnecting the SDH units SU#1 and SU#2 and connecting the SDH units SU#1 and SU#2 to the timing processors TC (W) and TC (P), respectively.
On the other hand, the Ethernet unit EU transmits/receives a signal to/from the network terminal equipments NTE1 and NTE2 at a line clock speed of 125 MHz (for FE) (or 1.25 GHz (for GbE) or 12.5 GHz (for 10 GbE)).
An arrangement of the above Ethernet unit EU depicted in FIG. 11 is depicted in FIG. 12. This Ethernet unit EU is composed of an interface portion IF formed of an optical module or the like and connected to an external portion, a physical layer processor PHY performing a physical layer processing for a received signal from an external Ethernet and performing a physical layer processing for a transmission signal such as transmitting a signal synchronized with a free-running transmission clock [125 MHz] from a transmission clock generator SGC, a packet processor PP connected to a packet switch SW through a main signal transmission line ML and performing a normal packet processing such as QoS (Quality of Service) processing for a packet and an OAM processor OP performing a processing of OAM (Operations Administration and Maintenance) packet obtained by the packet processor PP.
Thus, the Ethernet unit EU does not have a particular function for a clock synchronization, so that the signal transmission is made with a free-running clock. Therefore, the data transmission/reception between the SDH unit SU and the Ethernet unit EU is made asynchronously through routes not depicted.
As a reference art, there is a branch line LAN station connected to a trunk line LAN station, in which a clock recovery section extracts and recovers a clock from a reception signal from an upstream station; a decoder detects a symbol specific to the branch line LAN or the trunk line LAN based on serial/parallel conversion data with respect to the reception signal; a microprocessor discriminates an upstream station based on the result of detection; when the upstream station is the branch line LAN station and a concerned station is a master station, an output of an oscillator is used, when not the master station, a recovered clock is used and when the upstream station is the trunk line LAN station, the recovery clock is used for selection control as a master clock (see e.g. Japanese Laid-open Patent Publication No. 07-30569).
As a further reference art, there is a device, in which plural shelves have internal buses mounting and connecting plural units and connectors connected with both ends of these internal buses; a cascade connection is performed for the shelves for a master shelf by cables; by the timing control part of the master shelf, the extraction timing signal from the line stored in the master shelf; and an external timing signal and the extraction timing signal setting priority are selected based on a synchronizing state notification byte such as an S1 byte, etc. to generate a reference clock signal (see e.g. Japanese Laid-open Patent Publication No. 09-219687).